刁民的Blog

--by diaomin(www.diaomin.org)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ysq is
port
(
s0,s1,s2,cin,sel,start,clk :in std_logic;
din,reset : in std_logic_vector(7 downto 0);
rs0,rs1,wr :in std_logic;
cout ut std_logic;
result : out std_logic_vector(7 downto 0)
);
end ysq;
architecture cc of ysq is
signal ss1:std_logic_vector(2 downto 0);
signal ss2:std_logic_vector(1 downto 0);
type ysq_state is
(state0,state1,state2,state3,state4);
signal myysq:ysq_state;

begin
process (reset,clk,start)
variable r0,r1,r2,r3:std_logic_vector(7 downto 0);
variable a,b:std_logic_vector(7 downto 0);
variable data:std_logic_vector(7 downto 0);
variable outt:std_logic_vector(7 downto 0);
variable sint,aa,bb:std_logic_vector(8 downto 0);
variable din_temp :std_logic_vector(7 downto 0);
begin
ss1<=s2&s1&s0;
ss2<=rs1&rs0;
if clk'event and clk='1' then
case myysq is
when state0=>
r0:="00000000";
r1:="00000000";
r2:="00000000";
r3:="00000000";
din_temp:=din; --????????
when state1=>
if(ss2="00") then r0:=din_temp;
elsif(ss2="01") then r1:=din_temp;
elsif(ss2="10") then r2:=din_temp;--写入寄存器
else r3:=din_temp;
end if;
--if(reset='1') then myysq<=state0;
-- else myysq<=state1;
--end if;
when state2=>
if(wr='1') then
if(ss2="00") then data:=r0;
elsif(ss2="01") then data:=r1;
elsif(ss2="10") then data:=r2;--读出寄存器数据
else data:=r3;
end if;
result<=data;
else myysq<=state2;
--if(reset='1') then myysq<=state0;
--else myysq<=state3;
--end if;
end if;
when state3=>if(sel='1') then a:=data;
else b:=data;
end if;
if(start='1') then myysq<=state1;
else myysq<=state0;
end if;
--if(reset='1') then myysq<=state0;
--else myysq<=state4;
--end if;
when state4=>
case ss1 is
when "000"=> --清零
outt:="00000000";
cout<='0';
when "001" => --左移
outt:=a(6 downto 0)&'0';
when "010" => --右移
outt:='0'&a(7 downto 1);
when "011" => --加法
aa:='0'&a;bb:='0'&b;
sint:=aa+bb+cin;
cout<=sint( ;
outt:=sint(7 downto 0);
when "100" => --异或
outt:=a xor b;
when "101" => --或
outt:=a or b;
when "110" => --与
outt:=a and b;
when others=> --预置
outt:=a;

end case;
din_temp:=outt;
if(reset='1') then myysq<=state0;
else myysq<=state1;
end if;
end case;
end if;
end process ;

end cc;

标签：VHDL, 全加器

快速链接:http://www.diaomin.org/go/18561.html

Tags: